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| TC55VEM208ASTN40,55 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55VEM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 A standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC55VEM208ASTN is available in a plastic 32-pin thin-small-outline package (TSOP). FEATURES * * * * * * * Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum): 3.6 V 3.0 V 10 A 5 A * Access Times: TC55VEM208ASTN 40 Access Time CE OE 55 55 ns 55 ns 30 ns 40 ns 40 ns 25 ns Access Time Access Time * Package: TSOP 32-P-0.50 (Weight:0.22 g typ) PIN ASSIGNMENT (TOP VIEW) 32 PIN TSOP PIN NAMES A0~A18 Address Inputs Read/Write Control Output Enable Chip Enable Data Inputs/Outputs Power Ground 32 R/W OE CE 1 16 (Normal) 17 I/O1~I/O8 VDD GND Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 R/W 21 I/O1 6 A17 22 I/O2 7 A15 23 I/O3 8 VDD 24 GND 9 A18 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE 15 A5 31 A10 16 A4 32 OE 2002-08-07 1/11 TC55VEM208ASTN40,55 BLOCK DIAGRAM CE A7 A8 A9 A11 A12 A13 A14 A15 A16 A17 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER VDD GND MEMORY CELL ARRAY 2,048 x 256 x 8 (4,194,304) 8 DATA CONTROL SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A4 A5 A6 A10 OE R/W CE CE OPERATING MODE MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low CE OE R/W H L H * Output Input High-Z High-Z I/O1~I/O8 POWER IDDO IDDO IDDO IDDS L L L H L * H * MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~4.2 -0.3*~4.2 -0.5~VDD + 0.5 0.6 260 -55~150 -40~85 UNIT V V V W C C C *: -2.0 V when measured at a pulse width of 20ns 2002-08-07 2/11 TC55VEM208ASTN40,55 DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C) SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage VDD = 2.3 V~2.7 V VDD = 2.7 V~3.6 V MIN 2.3 2.0 2.2 -0.3* 1.5 VDD x 0.24 3.6 V V TYP MAX 3.6 VDD + 0.3 UNIT V V *: -2.0 V when measured at a pulse width of 20ns DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output Low Current Output Leakage Current VIN = 0 V~VDD TEST CONDITION MIN -0.5 2.1 MIN 1 s tcycle MIN 1 s TYP MAX UNIT 1.0 1.0 35 mA 8 30 mA 3 1 10 2 5 A mA A mA mA A Output High Current VOH = VDD - 0.5 V VOL = 0.4 V CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL 0.7 IDDO1 Operating Current IDDO2 CE = 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V CE = VIH IDDS1 VDD = Ta = -40~85C 3.3V 0.3 V Standby Current IDDS2 CE = VDD - 0.2 V Ta = 25C VDD =3.0 V Ta = -40~40C Ta = -40~85C CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2002-08-07 3/11 TC55VEM208ASTN40,55 (Ta = -40 to 85C, VDD = 2.7 to 3.6 V) READ CYCLE TC55VEM208ASTN SYMBOL PARAMETER MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 40 5 0 10 40 MAX 40 40 25 20 20 MIN 55 5 0 10 55 MAX 55 55 30 25 25 ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE TC55VEM208ASTN SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 40 30 35 0 0 0 20 0 40 MAX 20 MIN 55 40 45 0 0 0 25 0 55 MAX 25 ns UNIT tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-07 4/11 TC55VEM208ASTN40,55 (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) READ CYCLE TC55VEM208ASTN SYMBOL PARAMETER MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 55 5 0 10 40 MAX 55 55 30 25 25 MIN 70 5 0 10 55 MAX 70 70 35 30 30 ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE TC55VEM208ASTN SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 40 45 0 0 0 25 0 40 MAX 25 MIN 70 50 55 0 0 0 30 0 55 MAX 30 ns UNIT tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-07 5/11 TC55VEM208ASTN40,55 AC TEST CONDITIONS PARAMETER Input pulse level t R, t F Timing measurements Reference level Output load TEST CONDITION 0.2 V, VDD x 0.7 V + 0.2 V 1V / ns(Fig.1) VDD x 0.5 VDD x 0.5 30 pF + 1 TTL Gate(Fig.2) Fig.1 : Input rise and fall time Fig.2 : Output load VTM VDD Typ GND 10% 1 V/ns tR 90% 90% 10% 1 V/ns tF R1 Dout R1 = 810 R2 = 1610 VTM = 2.3 V R2 30 pF 2002-08-07 6/11 TC55VEM208ASTN40,55 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address A0~A18 tACC tCO CE tOH tOE OE tOD DOUT I/O1~8 tOEE tCOE Hi-Z VALID DATA OUT tODO Hi-Z WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW CE tWP tWR tODW DOUT I/O1~8 (See Note 2) Hi-Z tDS DIN I/O1~8 (See Note 5) tOEW (See Note 3) tDH (See Note 5) VALID DATA IN 2002-08-07 7/11 TC55VEM208ASTN40,55 WRITE CYCLE 2 (CE CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW CE tWP tWR tCOE DOUT I/O1~8 Hi-Z tODW Hi-Z tDS tDH (See Note 5) DIN I/O1~8 (See Note 5) VALID DATA IN Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2002-08-07 8/11 TC55VEM208ASTN40,55 DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C) SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.6 V IDDS2 Standby Current VDH = 3.0 V Ta = -40~85C Ta = -40~40C Ta = -40~85C MIN 1.5 0 5 TYP MAX 3.6 10 2 5 ns ms A UNIT V tCDR tR Chip Deselect to Data Retention Mode Time Recovery Time CE CONTROLLED DATA RETENTION MODE VDD VDD DATA RETENTION MODE 2.3 V (See Note) VIH tCDR CE (See Note) tR VDD - 0.2 V GND Note: When CE is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). 2002-08-07 9/11 TC55VEM208ASTN40,55 PACKAGE DIMENSIONS Weight:0.22 g (typ) 2002-08-07 10/11 TC55VEM208ASTN40,55 RESTRICTIONS ON PRODUCT USE 000707EBA * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2002-08-07 11/11 |
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